{"id":2020,"date":"2024-07-22T09:36:15","date_gmt":"2024-07-22T09:36:15","guid":{"rendered":"https:\/\/britainwriters.com\/answers\/?p=2020"},"modified":"2024-07-22T09:36:17","modified_gmt":"2024-07-22T09:36:17","slug":"design-and-implement-a-circuit-in-hdl-assignment","status":"publish","type":"post","link":"https:\/\/britainwriters.com\/answers\/design-and-implement-a-circuit-in-hdl-assignment\/","title":{"rendered":"Design And Implement A Circuit In HDL Assignment"},"content":{"rendered":"\n

Assignment Task<\/strong><\/h3>\n\n\n\n

Description<\/strong><\/p>\n\n\n\n

In-course assessment. Requires design implementation and testing of code written in HDL and assembly language<\/p>\n\n\n\n

Rationale<\/strong><\/p>\n\n\n\n

Provides an opportunity to write HDL and assembly code including understanding the implementation of branching and functions.<\/p>\n\n\n\n

Learning outcomes assessed<\/strong><\/p>\n\n\n\n

The basic building blocks of a computer in detail and explain how they are composed to construct computing machinery.<\/p>\n\n\n\n

Apply appropriate tools to develop, simulate and test logic circuits (CAD).<\/p>\n\n\n\n

Explain how high level programming constructs, such as \u2019if\u2019 statements and \u2019for\u2019 loops, are implemented at a machine level<\/p>\n\n\n\n

Assignment guidance<\/strong><\/p>\n\n\n\n

1. There are two sections to this resit assessment. Section I requires the implementation of HDL programs and Section II requires the implementation of assembly language.<\/p>\n\n\n\n

2. Assessment tasks<\/p>\n\n\n\n

Section I<\/strong><\/p>\n\n\n\n

Your task is to design and implement a circuit in hdl which takes two 2-bit numbers (A, B) and (C, D) as input and produces a 3-bit output (E, F, G).<\/p>\n\n\n\n

The final circuit has 6 inputs in total (f1, f0, A, B, C, D) and 3 outputs (E, F, G). The function of the circuit is determined by the two inputs f1 and f0.<\/p>\n\n\n\n

The truth tables below define the operation of the circuit for each combination of f1 and f0.<\/p>\n\n\n\n

Table 1: When <\/strong>f1 , f 0 = (1, 1) FZero<\/p>\n\n\n\n

A<\/td>B<\/td>C<\/td>D<\/td>F<\/td>G<\/td><\/tr>
0<\/td>0<\/td>0<\/td>0<\/td>1<\/td>1<\/td><\/tr>
0<\/td>0<\/td>0<\/td>1<\/td>1<\/td>0<\/td><\/tr>
0<\/td>0<\/td>1<\/td>0<\/td>0<\/td>1<\/td><\/tr>
0<\/td>0<\/td>1<\/td>1<\/td>0<\/td>0<\/td><\/tr>
0<\/td>1<\/td>0<\/td>0<\/td>1<\/td>1<\/td><\/tr>
0<\/td>1<\/td>0<\/td>1<\/td>1<\/td>0<\/td><\/tr>
0<\/td>1<\/td>1<\/td>0<\/td>0<\/td>1<\/td><\/tr>
0<\/td>1<\/td>1<\/td>1<\/td>0<\/td>0<\/td><\/tr>
1<\/td>0<\/td>0<\/td>0<\/td>1<\/td>1<\/td><\/tr>
1<\/td>0<\/td>0<\/td>1<\/td>1<\/td>0<\/td><\/tr>
1<\/td>0<\/td>1<\/td>0<\/td>0<\/td>1<\/td><\/tr>
1<\/td>0<\/td>1<\/td>1<\/td>0<\/td>0<\/td><\/tr>
1<\/td>1<\/td>0<\/td>0<\/td>1<\/td>1<\/td><\/tr>
1<\/td>1<\/td>0<\/td>1<\/td>1<\/td>0<\/td><\/tr>
1<\/td>1<\/td>1<\/td>0<\/td>0<\/td>1<\/td><\/tr>
1<\/td>1<\/td>1<\/td>1<\/td>0<\/td>0<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Table 2: When<\/strong> (f 1, f 0) = (1, 0) FOne<\/p>\n\n\n\n

A<\/td>B<\/td>C<\/td>D<\/td>F<\/td>G<\/td><\/tr>
0<\/td>0<\/td>0<\/td>0<\/td>0<\/td>0<\/td><\/tr>
0<\/td>0<\/td>0<\/td>1<\/td>0<\/td>0<\/td><\/tr>
0<\/td>0<\/td>1<\/td>0<\/td>0<\/td>0<\/td><\/tr>
0<\/td>0<\/td>1<\/td>1<\/td>0<\/td>0<\/td><\/tr>
0<\/td>1<\/td>0<\/td>0<\/td>0<\/td>0<\/td><\/tr>
0<\/td>1<\/td>0<\/td>1<\/td>0<\/td>1<\/td><\/tr>
0<\/td>1<\/td>1<\/td>0<\/td>0<\/td>0<\/td><\/tr>
0<\/td>1<\/td>1<\/td>1<\/td>0<\/td>1<\/td><\/tr>
1<\/td>0<\/td>0<\/td>0<\/td>0<\/td>0<\/td><\/tr>
1<\/td>0<\/td>0<\/td>1<\/td>0<\/td>0<\/td><\/tr>
1<\/td>0<\/td>1<\/td>0<\/td>1<\/td>0<\/td><\/tr>
1<\/td>0<\/td>1<\/td>1<\/td>1<\/td>0<\/td><\/tr>
1<\/td>1<\/td>0<\/td>0<\/td>0<\/td>0<\/td><\/tr>
1<\/td>1<\/td>0<\/td>1<\/td>0<\/td>1<\/td><\/tr>
1<\/td>1<\/td>1<\/td>0<\/td>1<\/td>0<\/td><\/tr>
1<\/td>1<\/td>1<\/td>1<\/td>1<\/td>1<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

 <\/h3>\n\n\n\n

Table3:When<\/strong> (f1,f0)=(0,1)FTwo <\/p>\n\n\n\n

A<\/td>B<\/td>C<\/td>D<\/td>F<\/td>G<\/td><\/tr>
0<\/td>0<\/td>0<\/td>0<\/td>0<\/td>0<\/td><\/tr>
0<\/td>0<\/td>0<\/td>1<\/td>0<\/td>1<\/td><\/tr>
0<\/td>0<\/td>1<\/td>0<\/td>1<\/td>0<\/td><\/tr>
0<\/td>0<\/td>1<\/td>1<\/td>1<\/td>1<\/td><\/tr>
0<\/td>1<\/td>0<\/td>0<\/td>0<\/td>1<\/td><\/tr>
0<\/td>1<\/td>0<\/td>1<\/td>0<\/td>1<\/td><\/tr>
0<\/td>1<\/td>1<\/td>0<\/td>1<\/td>1<\/td><\/tr>
0<\/td>1<\/td>1<\/td>1<\/td>1<\/td>1<\/td><\/tr>
1<\/td>0<\/td>0<\/td>0<\/td>1<\/td>0<\/td><\/tr>
1<\/td>0<\/td>0<\/td>1<\/td>1<\/td>1<\/td><\/tr>
1<\/td>0<\/td>1<\/td>0<\/td>1<\/td>0<\/td><\/tr>
1<\/td>0<\/td>1<\/td>1<\/td>1<\/td>1<\/td><\/tr>
1<\/td>1<\/td>0<\/td>0<\/td>1<\/td>1<\/td><\/tr>
1<\/td>1<\/td>0<\/td>1<\/td>1<\/td>1<\/td><\/tr>
1<\/td>1<\/td>1<\/td>0<\/td>1<\/td>1<\/td><\/tr>
1<\/td>1<\/td>1<\/td>1<\/td>1<\/td>1<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Table4:When<\/strong> (f1,f0)=(0,0 )FThree<\/p>\n\n\n\n

A<\/td>B<\/td>C<\/td>D<\/td>E<\/td>F<\/td>G<\/td><\/tr>
0<\/td>0<\/td>0<\/td>0<\/td>0<\/td>0<\/td>0<\/td><\/tr>
0<\/td>0<\/td>0<\/td>1<\/td>0<\/td>0<\/td>1<\/td><\/tr>
0<\/td>0<\/td>1<\/td>0<\/td>0<\/td>1<\/td>0<\/td><\/tr>
0<\/td>0<\/td>1<\/td>1<\/td>0<\/td>1<\/td>1<\/td><\/tr>
0<\/td>1<\/td>0<\/td>0<\/td>0<\/td>0<\/td>1<\/td><\/tr>
0<\/td>1<\/td>0<\/td>1<\/td>0<\/td>1<\/td>0<\/td><\/tr>
0<\/td>1<\/td>1<\/td>0<\/td>0<\/td>1<\/td>1<\/td><\/tr>
0<\/td>1<\/td>1<\/td>1<\/td>1<\/td>0<\/td>0<\/td><\/tr>
1<\/td>0<\/td>0<\/td>0<\/td>0<\/td>1<\/td>0<\/td><\/tr>
1<\/td>0<\/td>0<\/td>1<\/td>0<\/td>1<\/td>1<\/td><\/tr>
1<\/td>0<\/td>1<\/td>0<\/td>1<\/td>0<\/td>0<\/td><\/tr>
1<\/td>0<\/td>1<\/td>1<\/td>1<\/td>0<\/td>1<\/td><\/tr>
1<\/td>1<\/td>0<\/td>0<\/td>0<\/td>1<\/td>1<\/td><\/tr>
1<\/td>1<\/td>0<\/td>1<\/td>1<\/td>0<\/td>0<\/td><\/tr>
1<\/td>1<\/td>1<\/td>0<\/td>1<\/td>0<\/td>1<\/td><\/tr>
1<\/td>1<\/td>1<\/td>1<\/td>1<\/td>1<\/td>0<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Table 4:When<\/strong> (f1,f0)=(0,0 )FThree<\/p>\n\n\n\n

a) For each of the truth tables above, implement a logic circuit in HDL that will perform the function specified by the truth table. You should create one circuit for each truth table and test it produces the required output for that truth table. The circuit for each truth table should be named FZero, FOne, FTwo, FThree corresponding to the names of the truth tables given above and must have corresponding filenames FZero.hdl, FOne.hdl, FTwo.hdl, FThree.hdl.<\/p>\n\n\n\n

Each circuit must have four inputs named A, B, C and D. Chips FZero, FOne and FTwo will have two outputs (F,G). Chip FThree will have three outputs named E,F and G.<\/p>\n\n\n\n

You must only use the built-in AND, NAND, OR, NOR, NOT, Mux, XOR or DMux chips.<\/p>\n\n\n\n

The test files provided (.tst and .cmp) can be used to test each output of a chip. For example FZero1.tst tests the F output of the chip FZero.hdl and FZero2.tst tests the G output of FZero.hdl.<\/p>\n\n\n\n

b) Combine all four circuits into one circuit which takes all six inputs and three outputs and test it to ensure it produces the correct output depending on the value of the inputs f1 and f0. Call the chip FALL. You can test this chip using FALL.tst but may wish to create further tests before submission. The value of output is undefined (can be either 0 or 1) unless (f1, f0) = (0, 0)<\/p>\n\n\n\n

You must only use the built-in AND, NAND, OR, NOR, NOT, Mux, XOR or DMux chips.<\/p>\n\n\n\n

c) Stretch Activity When performing computational operations it is often useful to be able to exe- cute a sequence of operations, each one using the output of the previous step as an input to the next step. For example to OR 3 values X OR Y OR Z you might first calculate X ORY and then on the next step apply ORZ to the previous output (X OR Y ).<\/p>\n\n\n\n

For this task adapt the circuit FALL so that it can combine a sequence of operations defined by different values for f1 and f0 at each step, by enabling the outputs Ft and Gt of step t to be used (feedback) as the inputs for the next<\/p>\n\n\n\n

operation Ct+1 and Dt+1 for step t + 1. You should also add a further input (Load) to the chip which when Load = 1 will enable you to load new inputs to<\/p>\n\n\n\n

Ct and Dt and when set to 0 sets Ct+1 = Ft and Dt+1 = Gt. The Load input will allow you to manually set the values of C and D at the start and during the sequence if required.<\/p>\n\n\n\n

Call this chip FSEQ. You can test this chip using FSEQ.tst but may wish to create further tests before submission. You must only use the built-in AND, NAND, OR, NOR, NOT, Mux, DMux,<\/p>\n\n\n\n

XOR or DFF chips.<\/p>\n\n\n\n

Section II<\/strong><\/p>\n\n\n\n

The Feistel cipher is a symmetric block cipher encryption framework which is the basis of many modern day encryption algorithms. In this coursework you will implement a Feistel cipher system as a software implementation in both a high level language and Hack Assembly.<\/p>\n\n\n\n

In a Feistel cipher the plaintext, P, to be encrypted is split into two equal size parts<\/p>\n\n\n\n

L0 and R0 such that P = L0R0. A function F is applied to one half of the plaintext, combined with a key, and the result is XOR\u2019d with the other half of the plaintext.<\/p>\n\n\n\n

Feistel ciphers often employ multiple rounds of this scheme. In general the scheme works as follows, for all i = 0, . . . n,<\/p>\n\n\n\n

Li+1 =<\/sub>Ri<\/p>\n\n\n\n

Ri+1<\/sub> = Li \u2295F (Ri, Ki)<\/p>\n\n\n\n

To decrypt an encrypted message using this cipher we can apply the same procedure in reverse. For i = n, n   \u2212 1 , . . . , 0 ,<\/p>\n\n\n\n

Ri    Li+1<\/sub><\/p>\n\n\n\n

L=    Ri+1         <\/sub>\u2295F( Li+1<\/sub> , Ki)<\/p>\n\n\n\n

For this coursework, we are interested in the 16-bit Feistel cipher which uses 4 rounds.<\/p>\n\n\n\n

The function F(A, B) = A<\/p>\n\n\n\n

\u2295\u00acB.<\/p>\n\n\n\n

The keys are derived from a single 8-bit key K0 such that,<\/p>\n\n\n\n

K0 = b7b6b5b4b3b2b1b0<\/p>\n\n\n\n

K1 = b6b5b4b3b2b1b0b7<\/p>\n\n\n\n

K2 = b5b4b3b2b1b0b7b6<\/p>\n\n\n\n

K3 = b4b3b2b1b0b7b6b5<\/p>\n\n\n\n

a) Write a program (XOR.asm) in HACK assembly that implements an XOR function between two 16-bit values stored in RAM[3] and RAM[4] and stores the result in RAM[5].<\/p>\n\n\n\n

b) Write a program (Rotate.asm) in HACK assembly that implements an algorithm to rotate the bits of a 16-bit number left (Least Significant bit (LSb) to Most Significant bit (MSb)). The original number should be stored in RAM[3] the number of times to rotate the bits should be in RAM[4] and the result stored in<\/p>\n\n\n\n

RAM[5], i.e. 1010111100000000 rotated left 3 times would be 0111100000000101<\/p>\n\n\n\n

where the MSb is used to replace the LSb.<\/p>\n\n\n\n

c) Write a program (FeistelEncryption.asm) in HACK assembly, that implements the described Feistel encryption system. The initial key, K0, will be stored in RAM[1], and the 16-bit plaintext will be stored in RAM[2]. The result of the encryption should be stored in RAM[0].<\/p>\n","protected":false},"excerpt":{"rendered":"

Assignment Task Description In-course assessment. Requires design implementation and testing of code written in HDL and assembly language Rationale Provides an opportunity to write HDL and assembly code including understanding the implementation of branching and functions. Learning outcomes assessed The basic building blocks of a computer in detail and explain how they are composed to […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-2020","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"yoast_head":"\nDesign And Implement A Circuit In HDL Assignment - My Blog<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/britainwriters.com\/answers\/design-and-implement-a-circuit-in-hdl-assignment\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Design And Implement A Circuit In HDL Assignment - My Blog\" \/>\n<meta property=\"og:description\" content=\"Assignment Task Description In-course assessment. Requires design implementation and testing of code written in HDL and assembly language Rationale Provides an opportunity to write HDL and assembly code including understanding the implementation of branching and functions. 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Requires design implementation and testing of code written in HDL and assembly language Rationale Provides an opportunity to write HDL and assembly code including understanding the implementation of branching and functions. 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