EN0720 Develop their knowledge, skill, and resource and time management applied to advanced design tools and languages in an independent manner.
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Last Updated:
05-Sep-23
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Assignment - Design, Verification and Implementation of an FPGA-based Monitoring System
Learning Outcome 1: Appreciate the need for, and understand the use of system-level design languages such as System-Verilog.
Learning Outcome 2: Create and implement Register Transfer Level (RTL) designs from system-level specifications, by use of design methodologies, such as Algorithmic State Machines and implement designs using programmable hardware.